The design of an ASIC involves selecting cells from an ASIC library to implement the function of a circuit. Typically, each cell in the library is either a standard cell (LL) which operates at a relatively low speed, or a high speed cell (HS) which operates at a relatively high speed. Standard cells and high speed cells may be used in combination in the design of an ASIC. A high speed cell is constructed of low transistors.
To achieve performance gain high speed (HS) cells are partially on, even when there is no activity on the cell. This requires a static or ‘leakage’ current to be drawn. HS cells therefore consume more power than LL cells. It is therefore necessary to include an optimum number of HS cells such that the performance requirements of the circuit are met without exceeding the power goals of the circuit.
The speed at which an ASIC runs may be calculated using Static Timing Analysis (STA). STA calculates the speed of the ASIC using the characteristics of the cells incorporated in the design of the ASIC together with the resistance and capacitance of the wires that physically connect the cells.
A method currently used to optimise the number of HS cells in the design of an ASIC is to use a logic synthesis tool. A logic synthesis tool may select LL and HS cells during the synthesis of the design of an ASIC. The decision to use either an LL cell or an HS cell is based on a statistical estimate of the wire length used in the ASIC design. By estimating the wire length, the resistance and capacitance of the wires may be calculated which may then be used in Static Timing Analysis.
A disadvantage of allowing the logic synthesis tool to freely incorporate HS cells into the design of an ASIC, is that this may cause the synthesis tool to construct lower area or ‘slower’ architectures and to recover the area using HS cells. This can give a false impression of the true size of a design. A further disadvantage is that synthesis tools may fully populate long critical paths with HS cells where ideally the designer needs to add pipelining, thereby masking fundamental design issues.
Another method currently used to optimise the number of HS cells in an ASIC is to allow a placement tool to use both LL and HS cells. In this method the actual physical locations of the cells are determined and it is assumed that cells are connected with wires that have minimum horizontal and vertical distance in order to calculate the wire length. This is known as Steiner routing. A percentage error is added to the calculated length of wire in order to include an allowance for deviations from the minimum path of a wire.
A disadvantage of this method is that the percentage error that is added to the calculated wire length is often an over estimate. This results in the placement tool including more HS cells in the design of the ASIC than is actually needed.
Post route HS optimisation is a method of adjusting the number of HS cells after detailed routing of the ASIC has been completed. Post route HS optimisation involves some form of analysis to determine whether maximum transition times or maximum delay targets are met. Post route optimisation may therefore be used to adjust the number of HS cells after a placement tool has been used to incorporate HS and LL cells.
The advantage of adjusting the HS cells at this stage of the design of the circuit is that routing is not disturbed. The effect of changing the reference of a cell, for example from HS to LL may simply be tested by re-running STA.
Changing the reference of a cell during post route optimisation is carried out on a manual ad hoc basis. The cells that are changed are chosen by manual inspection of timing reports generated by STA. Current methods of post route HS optimisation are therefore extremely time consuming. Furthermore the degree to which the optimisation is performed is subject to manual error.
It is therefore an aim of embodiments of the present invention to overcome the above mentioned disadvantages by providing a method for optimising the use of HS cells to maximise the likelihood of meeting timing and power budgets.